1. Field of the Invention
The present invention relates to a system and method by which automatic reconfiguration, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided.
2. Background of the Prior Art
A field programmable gate array (FPGA) is a semiconductor device containing programmable logic components and programmable interconnects. The programmable logic components can be programmed to duplicate the functionality of basic logic gates such as AND, OR, XOR, and NOT, or more complex combinational functions such as decoders or simple math functions. In most FPGAs, these programmable logic components (or logic blocks, in FPGA parlance) also include memory elements, which may be simple flip-flops or more complete blocks of memories.
A hierarchy of programmable interconnects allows the logic blocks of an FPGA to be interconnected as needed by the system designer. These logic blocks and interconnects can be configured by programming the FPGA after the manufacturing process by the customer/designer (hence the term “field programmable”) so that the FPGA can perform whatever logical function is needed. EEPROM based FPGAs may only be programmed once, and thereafter do not need further programming. However, SRAM based FPGAs lose their configuration data when power is removed from the FPGA. These types of FPGAs must be reconfigured every time power is applied. The configuration data is typically stored in a non-volatile memory, such as an EEPROM or FLASH memory, and is loaded into the FPGA after power up. In many cases, this occurs automatically after the power supplies reach acceptable levels, thus, providing an instant-on solution similar to an ASIC.
A number of problems may arise with FPGAs that are configured in this manner. First, the initial configuration attempt may fail and the device may be left permanently in the unconfigured state. Second, the device may configure successfully only to lose configuration at a later time. Conventionally, the only solution to these problems is to add more intelligence to the board via a CPLD or processor to detect and recover from these error conditions. In itself, the processor provides a viable solution only if the FPGA being configured does not contain processor related glue logic. Otherwise, the processor would not have the supporting logic required to implement the configuration monitor function. If neither of these conventional approaches are utilized, a technician would be required to manually repair the board, such as by re-seating the board. In addition, under certain circumstances, software may wish to perform a race free reconfiguration of a non-volatile memory configured FPGA. An intelligent device, such as a processor, could perform this task, unless the FPGA contains glue logic that is needed in order for the processor to operate. Conventionally, reconfiguration of such a system was possible only if an extra device was added to the board, which provided the essential glue logic required to keep the processor up and running. Most board designs require some instant-on logic, such as glue logic. In addition, many board designs require a large FPGA that is under software control. Conventionally, the only way to provide such logic is by using additional non-programmable extra devices on the board.
Thus a need arises for a technique by which automatic reconfiguration, such as in case of lost configuration or configuration error, and software-controlled reconfiguration may be provided that does not require the use of additional devices.